It is conventionally known that a plurality of video signals input at any frame frequencies and frame phases are subjected to compression coding to be fetched into a storage device. The video signals are sent to the respective encoders via a frame memory. Writing into and reading from the frame memory are performed at respective timings. In this case, the encoders for performing compression coding on the video signals need to be supplied with a reference signal at independent timings, respectively, which causes an increase in circuit size.
For example, Patent Document 1 describes a technology which is configured by use of a frame memory and performs frame rate conversion assuming different output frame frequencies for input frame frequencies, respectively.